1. Field of the Invention
The present invention relates to methods of processing a semiconductor wafer in a deposition chamber to provide copper vias and trenches, and more particularly, to a method of processing a semiconductor wafer in a deposition chamber including the deposition of an adhesion layer for a barrier material.
2. Description of Related Art
Integrated circuit (IC) manufacturers have traditionally used aluminum and aluminum alloys, among other metals, as the conductive metal for interconnects in integrated circuits. However, concerns exist as to the ability of aluminum-based interconnect metallization to meet the demands of future IC designs requiring high circuit density. In recent years, IC manufacturers have turned to copper to replace aluminum and aluminum alloys for advanced microelectronic applications. This is because copper has a higher conductivity that translates to significant improvement in the interconnect performance. In addition, copper-based interconnects offer better electromigration resistance than aluminum, thereby improving the interconnect reliability. However, the implementation of copper faces certain challenges. For example, the adhesion of copper (Cu) to silicon dioxide (SiO2) and to other dielectric materials is generally poor due to the low enthalpy of formation of the associated Cu compounds. Poor adhesion results in the delamination of Cu from adjoining films during the manufacturing process. Also, Cu ions readily diffuse into SiO2 under electrical bias, and increase the dielectric electrical leakage between Cu lines even at very low Cu concentrations within the dielectric. In addition, if copper diffuses into the underlying silicon where the active devices are located, device performance can be degraded. Copper behaves as a defect in silicon resulting in the reduction of minority carrier lifetime, and hence, results in device degradation. Furthermore, copper will also react with silicon at relatively low temperature to form copper silicide, which increases contact resistance.
The development of Damascene processing has enabled the implementation of copper into interconnect metallization. It is often a preferred method because it requires fewer processing steps than conventional methods and offers higher yields. Damascene processing involves formation of inlaid metal lines in trenches and vias formed in a dielectric layer. Conductive materials, such as copper, are deposited in different and non-contiguous planes. The pathways that join various layers of conductors are referred to as vias, whereas the conductors within a layer are referred to as trenches. Insulators between trenches are called inter-metal dielectric (IMD) and the insulating layers separating planes of conductive material are referred to as the interlevel dielectric (ILD).
The problem of the high diffusivity of copper in silicon dioxide (SiO2), and in other IMDs/ILDs, remains of great concern. To deal with this issue, an integrated circuit substrate must be coated with a suitable barrier layer that encapsulates copper and blocks diffusion of copper atoms. The diffusion barrier, comprising both conductive and non-conductive materials, is typically formed over a patterned dielectric layer and prior to deposition of copper. The time, materials, and process complexity required to form a separate diffusion barrier layer introduces a significant cost to the overall fabrication procedure. Also, the thickness of the barrier, if too great, can create problems with subsequent copper coatings and filling of ultra-fine features—e.g. a sub-100 nm diameter via. Typical barrier materials tend to be much less conductive than copper. Hence, if the barrier inside a sub-100 nm diameter via is too thick, it reduces the available volume of copper within the features leading to increased resistance of the via that could offset the advantage offered by the use of copper. For instance, the International Technology Roadmap for Semiconductors requires that at the 45 nm node the barrier for copper at the intermediate wiring level be limited to 5 nm.
A typical Damascene process flow begins with formation of pathways in a previously formed dielectric layer. Dielectric surfaces to which the invention is applicable preferably include at least one of silicon dioxide, silicon nitride, silicon oxynitride, fluorinated silica glass, CORAL™ from Novellus Systems, Inc., BLACK DIAMOND™ from Applied Materials, Inc., SiLK™ from Dow Corning, Inc., and NANOGLASS™ of Nanopore, Inc., and the like. These pathways may be etched as trenches and vias in a blanket layer of dielectric such as silicon dioxide. The pathways define conductive routes between various devices on a semiconductor wafer. Copper provides the conductive paths of the semiconductor wafer. The adjacent dielectric layer and silicon devices must be protected from copper ions that might otherwise diffuse into the dielectric layer and/or silicon. To accomplish this, the process optionally includes depositing a thin diffusion barrier layer before deposition of copper. Typical materials for the diffusion barrier layer include tantalum (Ta), tantalum nitride (TaNx), tungsten (W), titanium (Ti), titanium nitride (TiN), and the like. Conventional barrier layers are typically formed by a physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) process. Preferably, the diffusion barriers formed on integrated circuit substrates are made between about 1 and 30 nm thick.
Electrolytic deposition methods are used to fill the conductive pathways with copper. Before inlaying the line paths with electrolytic deposition of copper, a conductive surface coating must be applied on top of the barrier layer because conventional barrier materials exhibit high electrical resistivity and hence, cannot transport current during electrolytic copper plating. Typically, a copper seed layer is deposited on the barrier layer. Usually, a PVD process deposits this seed layer. Next, a much thicker layer of copper is deposited on the seed layer by electroplating. After deposition of the copper is completed, the copper is planarized, generally by chemical mechanical planarization (CMP) and/or electropolishing down to the dielectric in preparation for further processing. Finally, a dielectric barrier layer, such as silicon nitride, is applied over the surface thereby encapsulating the exposed copper and dielectric surfaces. In subsequent processing, a newly laid inter-level dielectric layer is etched to form another series of via and trench features wherein the vias connect to the underlying copper conductive routes. Once again, a diffusion barrier is deposited on the etched features in the dielectric and is followed by deposition of a copper seed, electroplating, CMP, and deposition of the dielectric barrier. This process is repeated forming layers of electrically connected, but encapsulated, copper conductive routes. Thus, in the final structure, there is a diffusion barrier between adjoining copper conductive routes.
Although diffusion barriers can be broadly categorized as conductive and non-conductive, the conventional materials (mentioned above) used for diffusion barriers are often ten times to one hundred times as electrically resistant as the copper routes that they encapsulate. The continuing trend towards smaller features size in ICs requires that the thickness of the diffusion barrier also be reduced in order to minimize the contribution of electrical resistance of conventional diffusion barriers. Thus, the replacement of conventional diffusion barriers with newer materials that have reduced electrical resistance is appealing. This is because it would further improve the conductivity in the lines and vias, thereby increasing the speed of signal propagation compared to interconnect structures using conventional barriers. Furthermore, electrolytic plating of copper directly onto conductive barrier materials precludes the use of a separate copper seed layer, thereby simplifying the overall process. Amongst various candidate materials that could serve as directly plateable diffusion barriers, the use of ruthenium (Ru) and its compounds, such as ruthenium oxide (RuOx), is shown herein to be beneficial. Ruthenium and its oxide are known to be good diffusion barriers to copper migration. In addition, electrochemical deposition of copper onto ruthenium is known to be feasible.
However, the use of ruthenium and its compounds as diffusion barriers presents a few challenges. One of the critical attributes of any diffusion barrier is its adhesion to the adjoining dielectric material. The adhesion of noble metals such as ruthenium to the dielectric materials (such as SiO2) is poor, leading to mechanical instabilities during further processing. It would be desirable to determine a process wherein the adhesion of the directly plateable barrier material to the underlying dielectric is improved greatly so as to withstand damascene processing.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method of adhering directly plateable barrier materials to an underlying dielectric capable of withstanding damascene processing.
It is another object of the present invention to provide a method of blocking the open pores in dielectric substrates prior to the deposition of the plateable barrier.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.